1. Field of the Invention
This invention relates to a semiconductor device and a system including the semiconductor device, in particular, a semiconductor device that latches a plurality of control signals in synchronization with a clock signal.
2. Description of the Related Art
An Address signal including multiple bits, etc., is input to a semiconductor device, such as DRAM (Dynamic Random Access Memory), and is latched in synchronization with a clock signal inside the semiconductor device. Latch circuits that latch respective bits of the address signal are usually arranged together in one place, as described in patent document 1.
[Patent Document 1] Japanese Laid-Open Patent Publication No. 2002-237188
However, according to a layout of the semiconductor device described in patent document 1, the distance between an input terminal and a latch circuit is different for each of the bits. This results in a smaller latch margin, thus making the use of a high-speed clock signal difficult. Solving such a problem requires a specific layout such that some interconnects are detoured so that the distance between the input terminal and the latch circuit become equal for every bit. However, such a layout poses a problem that a chip area is increased and that current consumption grows larger because of charge/discharge through a parasitic capacitance created by detoured interconnects.